Large-scale and high-power computer systems consume great amounts of electrical power, and reducing this power consumption has become a key concern in system design. Various architectural features and interfaces have been developed to facilitate control and reduction of power consumption.
For example, the Advanced Configuration and Power Interface (ACPI) Specification (November, 2013) was developed by leading companies in the computer industry in order to establish common interfaces enabling robust operating system (OS)-directed motherboard device configuration and power management of both devices and entire systems. The ACPI Specification defines both global power states of the computer and specific power states of components, such as the processor (generally referred to as the central processing unit, or CPU). The processor states are referred to as C0, C1, C2, . . . , Cn, wherein C0 is an active power state in which the CPU executes instructions, and C1 through Cn refer to different sleeping states (also referred to as sleep levels), with progressively lower levels of power consumption and correspondingly greater exit latencies. To conserve power, the OS places the processor into one of the supported sleeping states when the processor is idle. To regulate power consumption of active processors in the C0 state, the ACPI Specification also defines means for processor clock throttling and different processor performance states P0, P1, . . . Pn.
The PCI Express® Base Specification (Revision 3.1, March, 2014) defines mechanisms that can be used on the PCI Express (PCIe) bus to coordinate power management with Endpoints on the bus. For example, section 6.18 of the specification describes a Latency Tolerance Reporting (LTR) mechanism, which enables Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex, so that power management policies for central platform resources can be implemented to consider Endpoint service requirements. (The Root Complex is not required to honor the requested service latencies, but is strongly encouraged to do so.)
As another example, section 6.19 in the PCIe specification describes an Optimized Buffer Flush/Fill (OBFF) Mechanism, which enables a Root Complex to report to Endpoints time windows when the incremental platform power cost for Endpoint bus mastering and/or interrupt activity is relatively low. Typically these windows correspond to times during which the host CPU(s), memory, and other central resources associated with the Root Complex are active to service some other activity, for example the operating system timer tick. An OBFF indication is a hint—Functions are still permitted to initiate bus mastering and/or interrupt traffic whenever enabled to do so, although this activity will not be optimal for platform power, and the specification suggests that it should be avoided.
A number of techniques have been described in the patent literature for power management involving input/output (I/O) components. For example, U.S. Patent Application Publication 2012/0324258 describes a method of regulating power states in a processing system in which a processor component reports a present processor power state to an input-output hub. The present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state.